| Speaker Name | Dr. Sergey Mosin |
| Title | Design-for-Testability Automation of Analog and Mixed-Signal Integrated Circuits |
Biography
Dr. Sergey Mosin received the Ph.D. degree and defended the D.Sc. degree in computer engineering from Vladimir State University in 2000 and 2013 respectively. He is an Associate Professor. He was acting head of computer engineering department and vice-rector for research of Vladimir State University from 2006 to 2012. He has published over 100 papers in CAD and VLSI design. His research interests focus on the design and test of mixed-signal integrated circuits, design automation and CAD tools. Dr. Sergey Mosin served as a Publicity Chair of IEEE East-West Design and Test Symposium. He is a member of the IEEE and the Test Technology Technical Council (TTTC) of the IEEE Computer Society.
Abstract
Testing takes an important place in the processes of electronic circuits design and implementation. About 40-60% of total time required to IC development is spent on test procedures. According to the “rule of ten“ the cost of testing is increased tenfold at each next manufacturing cycle. High expenditure is dealt with increasing a complexity of IC and complication of test related efforts. Therefore the increasing of efficiency in test preparation and realizing for analog and mixed-signal integrated circuits is actual task. The following factors provide complexity of IC testing: changes of technological processes, increasing the scale of integration, high functional complexity of developed devices, limited access to internal components of IC, etc. The reduction of test cost (both time and money) may be providing at development and application new efficient test strategies. Design-for-Testability (DFT) is one of the perspective approaches, which ensures a selection of proper test solution already at early stages of IC design.
This tutorial will focus on design-for-testability automation issues. The four key processes of design-for-testability automation will be considered: simulation, test generation, testing sub-circuits generation and decision making. Simulation provides calculation of main parameters and characteristics for a designed circuit using sets of mathematical models and methods for numerical modeling of electronic circuits. Test generation provides a selection of controlled parameters, test nodes and test stimuli for a designed circuit, fault dictionary construction and efficiency estimation for obtained test patterns. Testing sub-circuits generation provides selection and inclusion in original circuit some test structures (DFT-solution) for analog and digital sub-circuits ensuring reduction of test complexity for a manufactured mixed-signal integrated circuit on the whole. Decision making provides comparison of proposed DFT-solutions based on cost model and fault coverage, and selection the reasonable DFT-solution for a designed IC taking into account such features as used integrated technology for manufacturing, volume of production, chip area, wafer effective radius, etc.
Outline
Importance of IC testing
Methodology of design-for-testability automation
Approaches to testing analog sub–circuits
Approaches to testing digital sub–circuits