Proceedings of the
9th International Conference of Asian Society for Precision Engineering and Nanotechnology (ASPEN2022)
15 – 18 November 2022, Singapore
doi:10.3850/978-981-18-6021-8_OR-15-0005
Miniaturization of Phase-Difference-of-Arrival Based Visible Light Positioning Receiver Using Field Programmable Gate Arrays
1Singapore Institute of Manufacturing Technology, Agency of Science Technology and Research (A*STAR), 2 Fusionopolis Way, #08-04 Innovis, 138634, Singapore
2School of Electrical and Electronic Engineering, Nanyang Technological University, 639798, Singapore
3School of Microelectronics and Communication Engineering, Chongqing University, Chongqing 400044, P.R. China
ABSTRACT
Miniaturization of indoor visible light positioning (VLP) receiver plays a key role in advancing VLP towards practical usage. However, the current phase-difference-of-arrival (PDOA) algorithm for VLP is both time-consuming and power-hungry computing for an embedded system. In this paper, a low-complexity PDOA algorithm for VLP and its implementation on field programmable gate arrays (FPGA) board is presented. Considering the actual computing capability of embedded system, a low-complexity PDOA algorithm is designed. With the support of Xilinx design suite, an FPGA-based firmware is implemented to locate users by sequential means of 1) obtaining analog-digital converter signal 2) filtering and demodulation of signals using FPGA device for PDOA measurements of low-complexity. Last but not the least, a microprocessor is adopted to receive the PDOA estimation from FPGA chip for further trilateration and hence providing the positioning results. A real-time hardware-in-the-loop (HIL) simulation has been carried out to evaluate the feasibility and performance of the proposed embedded VLP receiver in term of its accuracy and real-time performance. The results successfully validated the proposed embedded VLP receiver using PDOA algorithm of low complexity.
Keywords: Visible light positioning (VLP), phase-difference-of-arrival (PDOA), Field programmable gate arrays (FPGA), visible light communication (VLC)
1Singapore Institute of Manufacturing Technology, Agency of Science Technology and Research (A*STAR), 2 Fusionopolis Way, #08-04 Innovis, 138634, Singapore
2School of Electrical and Electronic Engineering, Nanyang Technological University, 639798, Singapore
3School of Microelectronics and Communication Engineering, Chongqing University, Chongqing 400044, P.R. China
ABSTRACT
Miniaturization of indoor visible light positioning (VLP) receiver plays a key role in advancing VLP towards practical usage. However, the current phase-difference-of-arrival (PDOA) algorithm for VLP is both time-consuming and power-hungry computing for an embedded system. In this paper, a low-complexity PDOA algorithm for VLP and its implementation on field programmable gate arrays (FPGA) board is presented. Considering the actual computing capability of embedded system, a low-complexity PDOA algorithm is designed. With the support of Xilinx design suite, an FPGA-based firmware is implemented to locate users by sequential means of 1) obtaining analog-digital converter signal 2) filtering and demodulation of signals using FPGA device for PDOA measurements of low-complexity. Last but not the least, a microprocessor is adopted to receive the PDOA estimation from FPGA chip for further trilateration and hence providing the positioning results. A real-time hardware-in-the-loop (HIL) simulation has been carried out to evaluate the feasibility and performance of the proposed embedded VLP receiver in term of its accuracy and real-time performance. The results successfully validated the proposed embedded VLP receiver using PDOA algorithm of low complexity.
Keywords: Visible light positioning (VLP), phase-difference-of-arrival (PDOA), Field programmable gate arrays (FPGA), visible light communication (VLC)