doi:10.3850/978-981-08-7302-8_1406


Fast and Efficient Implementation of AES on FPGA using Polynomial Notation for Mix Column and Inverse Mix Column


N. Shylashree1, V. Sridhar2 and K. L. Prabhasa3

1Research Scholar (RNSIT), PESCE, Mandya, VTU, Karnataka, India.

2E & CE Department, PESCE, Mandya, Karnataka, India.

3E & CE Department, RNSIT, Bengaluru VTU, Karnataka, India.

ABSTRACT

In this paper, we have discussed the design and implementation of an Advanced Encryption Standard (AES) Algorithm using polynomial notation for mix column and inverse mix column. The experimental result shows that the reduction of execution time with increased speed trade off is area. It is highly suitable for wireless applications like mobile telephony. In this paper, we have discussed various methods for implementation of substitution byte transformation, inverse substitution byte transformation and key expansion, further to increase of speed of execution of algorithm. The AES Algorithm design can be implemented on FPGA (Field Programmable Gate Array) family of Virtex-2. AES design has been implemented using “XC2V8000” device and the package as “FF1517” with the device speed as “-5”. They are tested and verified using CHIPSCOPE pro. The result shows the 8% improvement in speed against the previous work.

Keywords: Cryptography, Rijndael, Encryption, AES, Security, Xilinx, VHDL.


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