Proceedings of the
9th International Conference of Asian Society for Precision Engineering and Nanotechnology (ASPEN2022)
15 – 18 November 2022, Singapore
doi:10.3850/978-981-18-5185-8_OR-11-0126

Development of a Novel Multifunctional Abbé-Free 12"-Wafer Measuring Stage for Semiconductor Manufacturing

Chen-Yu Liao1, Yu Hung1, Fu-Sheng Yang1 and Liang-Chia Chen1,a

1Department of Mechanical Engineering, National Taiwan University, No. 1, Section 4, Roosevelt Rd., Taipei City, 10617, Taiwan

ABSTRACT

To design and develop a novel multifunctional Abbé free 12" wafer measuring stage is presented in this paper. The developed stage is designed and optimized, to be capable of integrating various optical measuring functional modules for defect detection and classification, CD measurement, 3-D dimensional inspection, and surface spectrum measurement in automated optical test (AOI). In work, the Abbé-principle design is adopted to minimize the volumetric errors of the stage's motion. With the framework of the stage established, the automatic parametric design is implemented with finite element method software to determine the lightest weight design within the tolerance of deformation and modal of the system. Ultra-low thermal-expansion material (Ohara CCZ-HS) is used to form a novel three-dimensional coordinate reference datum module located in the center of the stage to establish a precise metrological coordinate system for the stage. Furthermore, three-axis laser interferometry is designed to measure and compensate the Abbé-free point of the working datum, in order to maximize its positioning accuracy. By doing so, the volumetric errors induced by the stage movement can be minimized, so the positioning accuracy of the three-axis stage can be significantly improved. This system can achieve a scanning speed of 100 mm/s, and within the 300 × 300 × 5 mm measuring range, the absolute spatial positioning error is less than 50 nm, which can satisfy most stop-and-scan metrological operations in semiconductor manufacturing processes.

Keywords: Co-planar Stage, Abbé errors, wafer Inspection, nanoscale measurement, semiconductors manufacturing



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