The explosive demand for increasing miniaturization of microelectronics devices as well as mobile communication systems as well as microsensors / microsystems diversity of shapes and functional capabilities with the evershrinking form factor, has forced electronic device manufacturers into emergency reaction-mode into only one concept of device to be “smaller – thinner – lighter – cheaper – faster.” The wafer-level package with simultaneous through silicon via (TSV) connection and cavity hermetic sealing by low-temperature solder bonding for microelectromechanical system (MEMS) device could become a best solution by using different microprocessing technologies. Wet etching technique combined with dry etching technique is utilized to achieve a “Y-shaped” through wafer interconnection structure to shorten the TSV in order to reduce cost. Laser via drilling is a more performant but a simplified process compared to traditional photolithography methods. A reduction in process steps decreases overall costs and increases process yields.
These are also the main drivers for all of the major high integration devices packaging applications, including wafer level chip-scale package (WL-CSP),technologies of fan-out wafer level packaging (FOWLP) solution that provides significant bandwidth, performance, form factor and cost benefits compared to other packaging technologies available and flip-chip products (FCP).
Since each of these drivers adds increased complexity and challenges to the fabrication process, it is understandable that the top-level demand by the industry is mitigating risks caused by the added complexity, while at the same time managing costs.